ICS854057 datasheet(10/13 Pages) ICST

10 / 13 page

854057AG

www.icst.com/products/hiperclocks.html

REV. A JULY 18, 2005

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH

INTERNAL INPUT TERMINATION

SCHEMATIC EXAMPLE

Figure 4shows a schematic example of the ICS854057. In this

example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are

FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC

used. The decoupling capacitors should be physically located

near the power pin.

INPUTS:

PCLK/nPCLK INPUT:

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1k

Ω resistor can be tied

from PCLK to ground.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS OUTPUT

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

(U1,20)

680

Zo = 50

VDD

680

Zo = 50

100

680

ICS854057

VDD

PCLK0

VT0

nPCLK0

SEL1

SEL0

PCLK1

VT1

nPCLK1

GND

nPCLK2

VT2

PCLK2

VDD

PCLK3

VT3

nPCLK3

Zo = 50

VDD

LVDS

680

Zo = 50

VDD

VD D=2.5V

LVDS

LVPECL

0.1u

(U1,1)

0.1u

ICS854057 Datasheet(PDF) 10 Page - Integrated Circuit Systems

ICS854057 Datasheet(HTML) 10 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL