FUSB307BMPX datasheet(7/57 Pages) ONSEMI

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FUSB307B

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I2C Interface

The FUSB307B includes a full I2C slave controller. The

I2C slave fully complies with the I2C specification version

6 requirements. This block is designed for fast mode plus

signals.

Examples of an I2C write and read sequence are shown in

Figure 7 and Figure 8 respectively.

WR A

A P

NOTE:

Single Byte read is initiated by Master with P immediately following first data byte.

8bits

Write Data K+2

Slave Address

Write Data

Write Data K+1

Write Data K+N−1

WR A

A S

RD A

NA P

8bits

NOTE:

If Register is not specified Master will begin read from current register. In this case only sequence showing in Red

bracket is needed.

Single or multi byte read executed from current register location

(Single Byte read is initiated by Master with NA immediately following first data byte)

Read Data K+1

Read Data K+N−1

8bits

Slave Address

Read Data K

Slave Address

From Master to Slave

Start Condition

NA NOT Acknowledge (SDA High)

Read =1

From Slave to Master

Acknowledge (SDA Low)

WR Write = 0

Stop Condition

Figure 6. I2C Write Example

Figure 7. I2C Read Example

I2C Address Selection

I2C Slave addresses can be changed by configuring the

I2C_ADDR_GPO input on power up with a pull−up or

pull−down resistor and routing the SCL and SDA lines

according to Table 3.

Interrupt Operation

The INT_N pin is an active low, open drain output which

indicates to the host processor that an interrupt has occurred

in the FUSB307B which needs attention. The INT_N pin is

asserted after power−up or device reset RESET.SW_RES

set

(due

ALERTL.I_PORT_PWR

and

PWRSTAT.TCPC_INIT).

When an interruptible event occurs, INT_N is driven low

and is high−Z again when the processor clears the interrupt

by writing a 1 to the corresponding interrupt bit position.

Writing a 0 to an interrupt bit has no effect.

A processor firmware has additional control of INT_N

through individual event mask bits which can be set or

cleared to enable or disable INT_N from being driven low

when each event occurs.

Table 3. I2C ADDRESSES

I2C_ADDR

SCLx/SDAx

Slave Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCL1/SDA1

R/W

SCL1/SDA1

R/W

SCL2/SDA2

R/W

SCL2/SDA2

R/W

I2C Idle Mode

Entering I2C Idle Mode

The FUSB307B does not need to enter I2C Idle Mode in

order to save power. Entering this mode has no effect on I2C

function. The FUSB307B can enter idle mode if 0xFF is

written to the COMMAND register. Once in Idle mode, the

FUSB307B will not set the PWRSTAT.TCPC_INIT to one.

Exiting I2C Idle Mode

The FUSB307B will exit I2C Idle mode when any I2C

communication

addressed

the

slave.

The

ALERTL.I_PRT_PWR interrupt will be set and no

PWRSTAT bits will be set.

The device’s I2C block is always on without power

penalties.

FUSB307BMPX Datasheet(PDF) 7 Page - ON Semiconductor

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