MMPF0200F4ANES datasheet(78/114 Pages) NXP

78 / 114 page

NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Figure 21. VSNVS supply switch architecture

Table 92 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system.

VSNVS control

The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 93.

VSNVS external components

Table 92. VSNVS modes of operation

VSNVSVOLT[2:0]

VIN

MODE

110

> VTH1

VIN LDO 3.0 V

110

< VTL1

Coin cell switch

000 – 101

> VTH0

VIN LDO

000 – 101

< VTL0

Coin cell LDO

Table 93. Register VSNVSCTL - ADDR 0x6B

Name

Bit #

R/W

Default

Description

VSNVSVOLT

2:0

R/W

0x80

Configures VSNVS output voltage.(67)

000 = 1.0 V

001 = 1.1 V

010 = 1.2 V

011 = 1.3 V

100 = 1.5 V

101 = 1.8 V

110 = 3.0 V

111 = RSVD

UNUSED

7:3

–

0x00

UNUSED

Notes

67.

Only valid when a valid input voltage is present.

Table 94. VSNVS External Components

Capacitor

Value (

μF)

VSNVS

0.47

LDO\

PF0200

VSNVS

Coin Cell

1.8 - 3.3 V

VIN

2.25 V (VTL0) -

4.5 V

LICELL

Charger

LDO/SWITCH

VREF

Input

Sense/

Selector

I2C Interface

MMPF0200F4ANES Datasheet(PDF) 78 Page - NXP Semiconductors

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