AD9528BCPZ datasheet(58/67 Pages) AD

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AD9528

Data Sheet

Rev. D | Page 58 of 67

Table 53. PLL2 Loop Filter Control

Table 54. PLL2 Input Divider (R1) (Register 0x0207)

Bits

Bit Name

Description

[7:5]

Reserved

Reserved.

[4:0]

5-bit R1 divider

Divide by 1 to divide by 31.

00000, 00001 = divide by 1.

Table 55. PLL2 Feedback Divider (N2) (Register 0x0208)

Bits

Bit Name

Description

[7:0]

8-bit N2 divider

Division = Channel Divider Bits[7:0] + 1. For example, [7:0] = 0 is divided by 1, [7:0] = 1 is

divided by 2…[7:0] = 255 is divided by 256.

Table 56. PLL2 R1 Reference Divider (Register 0x0208 and Register 0x0209)

Address

Bits

Bit Name

Description

0x0209

Reserved

Reserved.

N2 divider power-down

0: (default) normal operation.

1: N2 divider powered down

[5:0]

N2 phase, Bits[5:0]

Divider initial phase after a sync is asserted relative to the divider input clock (from the

VCO divider output). LSB = ½ of a period of the divider input clock.

Phase 0 = no phase offset.

Phase 1 = ½ period offset.

…

Phase 63 = 31.5 period offset.

Address

Bits

Bit Name

Description

0x0205

[7:6]

RPOLE2 (Ω), Bits[1:0]

Bit 7

Bit 6

RPOLE2 (Ω)

900

450

300

225

[5:3]

RZERO (Ω), Bits[1:0]

Bit 5

Bit 4

Bit 3

RZERO (Ω)

3250

2750

2250

2100

3000

2500

2000

1850

[2:0]

CPOLE1 (pF), Bits[1:0]

Bit 2

Bit 1

Bit 0

CPOLE1 (pF)

0x0206

[7:1]

Reserved

Reserved.

Bypass internal RZERO resistor

Bypasses the internal RZERO resistor (RZERO = 0 Ω). Requires the use of a series external

zero resistor. This bit is the MSB of the loop filter control register (Register 0x0205 and

1 = internal RZERO bypassed.

0 = internal RZERO used.

AD9528BCPZ Datasheet(PDF) 58 Page - Analog Devices

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