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GM76V256C Datasheet(PDF) 2 Page - Hynix Semiconductor |
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GM76V256C Datasheet(HTML) 2 Page - Hynix Semiconductor |
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2 / 11 page ![]() GM76V256C Series Rev 02 / Apr. 2001 2 DESCRIPTION The GM76V256C is a high-speed, low power and 32,786 X 8-bits CMOS Static Random Access Memory fabricated using Hynix's high performance CMOS process technology. It is suitable for use in low voltage operation and battery back-up application. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0 volt. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Low power consumption • Battery backup(L/LL-part) - 2.0V(min.) data retention • Standard pin configuration - 28 pin 600mil PDIP - 28 pin 330mil SOP - 28 pin 8x13.4 mm TSOP-I (Standard) Product Voltage Speed Operation Standby Current(uA) Temperature No. (V) (ns) Current(mA) L LL ( °C) GM76V256C 3.3 85/100 2 20 10 0~70(Normal) GM76V256CE 3.3 85/100 2 30 15 -25~85(Extended) Note 1. Current value is max. PIN CONNECTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /WE A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /WE A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 /OE A11 A9 A8 A13 /WE Vcc A14 A12 A7 A6 A5 A4 A3 I/O8 PDIP SOP TSOP-I(Standard) PIN DESCRIPTION BLOCK DIAGRAM Pin Name Pin Function /CS Chip Select /WE Write Enable /OE Output Enable A0 ~ A14 Address Inputs I/O1 ~ I/O8 Data Input/Output Vcc Power Vss Ground A14 A0 ROW DECODER MEMORY ARRAY 512x512 I/O1 I/O8 /CS /OE /WE |
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