LTC2644 datasheet(13/20 Pages) AD

13 / 20 page

LTC2644

Rev. B

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OPERATION

The LTC2644 is a family of dual PWM input, voltage output

DACs in a 12-lead MSOP package. The part measures the

pulse width and period of the PWM inputs and updates

each DAC output after the corresponding PWM input

rising edge. Each DAC can operate rail-to-rail using an

external reference, or with a 2.5V full-scale voltage using

an integrated reference. Three resolutions (12-, 10-, and

8-bit) are available.

PWM-to-Voltage Conversion

The LTC2644 converts a PWM input to an accurate, sta-

ble, buffered voltage without the latency, slow settling,

and high-value passive components required for discrete

solutions. The PWM input pins (INX) accept frequencies

from 30Hz up to 6.25kHz (12-bit), 25kHz (10-bit), or

100kHz (8-bit).

The duty cycle is calculated after each PWM input rising

edge based upon the previous high and low pulse width.

The resulting digital DAC code k is calculated as:

k = 2N • tPWHX / tPERX

where tPWHX is the pulse width of the preceding INX period

and tPERX is the time between the two most recent INX

rising edges. The digital-to-analog transfer function is:

VOUT(IDEAL) =

⎛

⎝⎜

⎞

⎠⎟

VREF, for k = 0 to 2

N – 1

where N is the resolution, VREF is 2.5V for internal reference

mode or the REF pin voltage for external reference mode.

DAC Update Timing

The update for DAC output VOUTX occurs following each

rising edge input on INX (Figure 1a). Delay tS is the delay

from an INX rising edge to the VOUTX settled output volt-

age corresponding to the previous period’s duty cycle.

Delay tS is composed of the computational cycle delay (t4)

and the actual settling of the output DAC. The PWM-to-

binary, internal computational cycle begins immediately

following the INX rising edge. The computational cycle

is completed after delay t4 and the DAC output VOUTX is

updated. The DAC output typically settles to 12-bit accu-

racy within 8µs from the INX rising edge.

PWM Input Idle Mode Selection

When no PWM input rising edge is received for more than

the idle mode timeout delay t3 (nominal delay is 60ms),

the DAC output enters an idle mode state which can be

configured by connecting IDLSEL to GND or VCC accord-

ing to Table 1 below. Note that these pins also control the

initial state of the DACs after power-on reset.

Table 1. Power-On Reset and Idle Mode States

IDLSEL

Power-On Reset

INX Idle Low

INX Idle Hi

GND

Zero-Scale

Full-Scale

VCC

Power-Down Hi-Z

Hold

Transparent Operation

For applications in which the PWM input duty cycle may

be 0% or 100%, connect IDLSEL to GND to select trans-

parent operation, in which case an idle low input sets the

DAC to zero-scale or an idle high input sets the DAC to

full-scale. Figure 1c illustrates the timing for transparent

operation. Any pair of PWM input rising edges separated

by less than the idle mode timeout delay t3 (50ms mini-

mum) will cause the DAC code to be updated following

the second rising edge. Note that an idle high input state

may be followed by an idle low input state.

Sample/Hold Operation

The LTC2644 has the capability to sample the pulse-

width/period and hold the corresponding voltage level

indefinitely. Unlike analog filter implementations which

require the PWM input to run continuously, the LTC2644

may operate with a discontinuous PWM input. Connect

IDLSEL to VCC to select sample/hold operation, in which a

single pair of rising edges is sufficient to update the DAC,

and the DAC code retains its previous value when the

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