AD5683RARMZ datasheet(25/28 Pages) AD

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Data Sheet

AD5683R/AD5682R/AD5681R/AD5683

Rev. D | Page 25 of 28

Readback Input Register

The AD5683R allows readback of the contents of the input

as shown in Figure 53.

The SDO pin is automatically enabled for the duration of the

read operation, after which it is disabled again, as shown in

Table 15. If the DCEN bit was enabled before the read operation,

the bit is reset after a readback operation. If the AD5683R was

operating in daisy-chain mode, the user must enable the DCEN

bit again.

Table 15. Write and Readback sequence

SDI

SDO

Action

0x180000

0x000000

Write 0x8000 to the input register

0x500000

0x000000

Prepare data read from the input register

0x000000

0xX8000X1

Clock out the data

X mean don’t care.

HARDWARE LDAC

The DACs of the AD5683R/AD5682R/AD5681R/AD5683 have

a double buffered interface consisting of an input register and a

DAC register. The LDAC transfers data from the input register

to the DAC register and, consequently, the output is updated.

Hold LDAC high while data is clocked into the input shift

SYNC is taken high. The output DAC is updated on the falling

edge of LDAC.

If LDAC is pulsed while the data is being clocked, the pulse is

ignored.

HARDWARE RESET

RESET is an active low signal that sets the input and DAC

registers to zero scale and the control registers to their default

values. It is necessary to keep RESET low for 75 ns to complete

the operation. When the RESET signal returns high, the output

remains at the zero scale until a new value is programmed.

While the RESET pin is low, the AD5683R/AD5681R ignore

any new command.

If RESET is held low at power-up, the internal reference is not

initialized correctly until the RESET pin is released.

SYNC

SCLK

DB23

DB0

DB23

DB0

SDI

NOP CONDITION

READBACK COMMAND

DB23

DB0

SDO

DATA

Figure 53. Readback Operation

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