AD5317R datasheet(21/28 Pages) AD

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Data Sheet

AD5317R

Rev. B | Page 21 of 28

23B

STANDALONE OPERATION

The write sequence begins by bringing the

SYNCE

line low. Data

from the SDIN line is clocked into the 24-bit input shift register

on the falling edge of SCLK. After the last of the 24 data bits is

clocked in,

SYNCE

should be brought high. The programmed

function is then executed, that is, an

LDACE

-dependent change

in DAC register contents and/or a change in the mode of

operation. If

SYNCE

is taken high before the 24th clock, invalid

data may be loaded to the DAC.

SYNCE

must be brought high

for a minimum of 20 ns (single channel, see t8 in Figure 2)

before the next write sequence so that a falling edge of

SYNCE

can initiate the next write sequence.

SYNCE

should be idled at

the rails between write sequences for even lower power opera-

tion of the part. The

SYNCE

line is kept low for 24 falling edges

of SCLK, and the DAC is updated on the rising edge of

SYNCE

After the data is transferred into the input register of the

addressed DAC, all DAC registers and outputs can be updated

by taking

LDACE

low while the

SYNCE

line is high.

24B

WRITE AND UPDATE COMMANDS

45B

Write to Input Register n (Dependent on

LDACE

)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When

LDACE

is low,

the input register is transparent (if not controlled by the

LDACE

mask register).

46B

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected and updates the DAC

outputs directly.

47B

Write to and Update DAC Channel n (Independent

LDACE

)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly.

25B

DAISY-CHAIN OPERATION

For systems that contain several DACs, the SDO pin can be

used to daisy-chain several devices together. This function

is enabled through a software executable daisy-chain enable

(DCEN) command. Command 1000 is reserved for this DCEN

function (see Table 8). The daisy-chain mode is enabled by

setting Bit DB0 in the DCEN register. The default setting is

standalone mode, where DB0 = 0. Table 10 shows how the state

of the bit corresponds to the mode of operation of the device.

Table 10. Daisy-Chain Enable (DCEN) Register

DB0

Description

Standalone mode (default)

DCEN mode

68HC11*

MISO

SDIN

SCLK

MOSI

SCK

PC7

PC6

SDO

SCLK

SDO

SCLK

SDO

SDIN

SYNC

LDAC

AD5317R

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 45. Daisy-Chaining the AD5317R

The SCLK pin is continuously applied to the input shift register

when

SYNCE

is low. If more than 24 clock pulses are applied, the

data ripples out of the input shift register and appears on the

SDO line. This data is clocked out on the rising edge of SCLK

and is valid on the falling edge. By connecting the SDO line to

the SDIN input on the next DAC in the chain, a daisy-chain

interface is constructed. Each DAC in the system requires 24

clock pulses. Therefore, the total number of clock cycles must

equal 24 × N, where N is the total number of devices that are

updated. If

SYNCE

is taken high at a clock that is not a multiple

of 24, invalid data may be loaded to the DAC. When the serial

transfer to all devices is complete,

SYNCE

is taken high. This

latches the input data in each device in the daisy chain and

prevents any further data from being clocked into the input

shift register. The serial clock can be a continuous or a gated clock.

A continuous SCLK source can be used only if

SYNCE

can be

held low for the correct number of clock cycles. In gated clock

mode, a burst clock containing the exact number of clock cycles

must be used, and

SYNCE

must be taken high after the final clock

to latch the data.

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