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AD5601/AD5611/AD5621

Data Sheet

Rev. H | Page 14 of 21

THEORY OF OPERATION

DAC SECTION

The AD5601/AD5611/AD5621 DACs are fabricated on a

CMOS process. The architecture consists of a string DAC

followed by an output buffer amplifier. Figure 39 is a block

diagram of the DAC architecture.

Figure 39. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by

















OUT

where:

is the decimal equivalent of the binary code that is loaded to

the DAC register.

is the bit resolution of the DAC.

RESISTOR STRING

The resistor string structure is shown in Figure 40. It is simply a

string of resistors, each of Value R. The code loaded to the DAC

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaran-

teed monotonic.

Figure 40. Resistor String Structure

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, giving an output range of 0 V to VDD. It is

capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

are shown in Figure 25. The slew rate is 0.5 V/µs, with a half-

scale settling time of 8 µs with the output loaded.

SERIAL INTERFACE

The AD5601/AD5611/AD5621 have a 3-wire serial interface

(SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI,

and MICROWIRE interface standards as well as most DSPs. See

Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the SDIN line is clocked into the 16-bit shift register on

the falling edge of SCLK. The serial clock frequency can be as

high as 30 MHz, making the AD5601/AD5611/AD5621 com-

patible with high speed DSPs. On the 16th falling clock edge,

the last data bit is clocked in and the programmed function is

executed (a change in DAC register contents and/or a change

in the mode of operation). At this stage, the SYNC line may be

kept low or brought high. In either case, it must be brought high

for a minimum of 20 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 1.8 V

than it does when VIN = 0.8 V, SYNC should be idled low

between write sequences for even lower power operation of the

part, as mentioned previously. However, it must be brought

high again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 41). The first

two bits are control bits, which control the operating mode of

the part (normal mode or any one of three power-down

modes). For a complete description of the various modes, see

the Power-Down Modes section. For the AD5621, the next

12 bits are the data bits, which are transferred to the DAC

the last two bits is ignored by the AD5621. See Figure 42 and

Figure 43 for the AD5611 and AD5601 input shift register map.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 16 falling edges of SCLK and the DAC is updated on the

16th falling edge. However, if SYNC is brought high before the

16th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 44).

VDD

VOUT

GND

RESISTOR

NETWORK

REF (+)

REF (–)

OUTPUT

AMPLIFIER

DAC REGISTER

TO OUTPUT

AMPLIFIER

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