AD5663R datasheet(21/32 Pages) AD

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Data Sheet

AD5623R/AD5643R/AD5663R

Rev. G | Page 21 of 32

THEORY OF OPERATION

DIGITAL-TO-ANALOG SECTION

The AD5623R/AD5643R/AD5663R DAC is fabricated on

a CMOS process. The architecture consists of a string DAC

followed by an output buffer amplifier. Figure 49 shows a block

diagram of the DAC architecture.

DAC

RESISTOR

STRING

REF (+)

VDD

GND

REF (–)

VOUT

OUTPUT

AMPLIFIER

(GAIN = +2)

Figure 49. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

















REFIN

OUT

The ideal output voltage when using the internal reference is

given by

















REFOUT

OUT

where:

is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 4095 for AD5623R (12-bit)

0 to 16,383 for AD5643R (14-bit)

0 to 65,535 for AD5663R (16-bit)

is the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 50. It is simply a

string of resistors, each of Value R. The code loaded to the DAC

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. It can drive

a load of 2 kΩ in parallel with 1000 pF to GND. The source and

sink capabilities of the output amplifier can be seen in Figure 31.

The slew rate is 1.8 V/µs with a 1/4 to 3/4 full-scale settling time

of 10 µs.

TO OUTPUT

AMPLIFIER

Figure 50. Resistor String

INTERNAL REFERENCE

The AD5623R/AD5643R/AD5663R on-chip reference is off at

power-up and is enabled via a write to a control register. See the

Internal Reference Setup section for details.

The AD5623R-3/AD5643R-3/AD5663R-3 has a 1.25 V,

5 ppm/°C reference, giving a full-scale output of 2.5 V. The

AD5623R-5/AD5643R-5/AD5663R-5 has a 2.5 V, 5 ppm/°C

reference, giving a full-scale output of 5 V. The internal

reference associated with each part is available at the VREFOUT

pin. A buffer is required if the reference output is used to drive

external loads. When using the internal reference, it is

recommended that a 100 nF capacitor be placed between

reference output and GND for reference stability.

EXTERNAL REFERENCE

The VREFIN pins on the AD5623R-3/AD5643R-3/AD5663R-3

and the AD5623R-5/AD5643R-5/AD5663R-5 allows the use of

an external reference if the application requires it. The on-chip

reference is off at power-up, and this is the default condition.

The AD5623R-3/AD5643R-3/AD5663R-3 and the AD5623R-5/

AD5643R-5/AD5663R-5 can be operated from a single 2.7 V to

5.5 V supply.

SERIAL INTERFACE

The AD5623R/AD5643R/AD5663R have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and

MICROWIRE interface standards, as well as with most DSPs.

See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible

with high speed DSPs. On the 24th falling clock edge, the last

data bit is clocked in and the programmed function is executed,

for example, a change in DAC register contents and/or a change

in the mode of operation.

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