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DS3112

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2.4 T3/E3 Transmit Formatter Signal Description

Signal Name:

FTSOF

Signal Description:

T3/E3 Trans mit Formatter Start Of Frame Sync Signal

Signal Type:

Output/Input

This signal can be configured via the FTSOFC control bit in Master Control Register 1 to be either an

output or an input. When this signal is an output, it pulses for one FTCLK period to indicate a T3 or E3

frame boundary (Figure 2.4A). When this signal is an input, it is sampled to set the transmit T3 or E3

frame boundary (Figure 2.4A). This signal can be configured via the FTSOFI control bit in Master

Control Register 3 (Section 4.2) to be either active high (normal mode) or active low (inverted mode).

Signal Name:

FTCLK

Signal Description:

T3/E3 Transmit Formatter Clock

Signal Type:

Input

An accurate T3 (44.736MHz ±20ppm) or E3 (34.368MHz ±20ppm) clock should be applied at this signal.

This signal is used to clock data into the transmit T3/E3 formatter. Transmit data can be clocked into the

device either on a rising edge (normal mode) or a falling edge (inverted mode). This option is controlled

via the FTCLKI control bit in Master Control Register 3 (Section 4.2).

Signal Name:

FTD

Signal Description:

T3/E3 Transmit Formatter Serial Data

Signal Type:

Input

This signal inputs data into the transmit T3/E3 formatter. This signal can be sampled either on the rising

edge of FTCLK (normal mode) or the falling edge of FTCLK (inverted mode). This option is controlled

via the FTCLKI control bit in Master Control Register 3 (Section 4.2). Also, the data input to this signal

can be internally inverted if enabled via the FTDI control bit in Master Control Register 3 (Section 4.2).

When T3 C-Bit Parity Mode is disabled, C Bits are sampled at this input. This signal is ignored when the

M13/E13 multiplexer is enabled. (See the UNCHEN control bit in Master Control Register 1.) If not

used, this signal should be tied low.

Signal Name:

FTDEN

Signal Description:

T3/E3 Transmit Formatter Serial Data Enable or Gapped Clock Output

Signal Type:

Output

Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a

data enable or a gapped clock. In the data enable mode, this signal will go active when payload data

should be made available at the FTD input. In the gapped clock mode, this signal will act as a demand

clock for the FTD input and it will transition for each bit of payload data needed at the FTD input and it

will be suppressed when the transmit formatter inserts overhead data and hence no data is needed at the

FTD input. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X Bits, and P Bits. In

the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits 1 to 12). See Figure

2.4A for an example. his signal can be internally inverted if enabled via the FTDENI control bit in

Master Control Register 3 (Section 4.2). This signal operates in the same manner even when the device is

configured in the Transmit Pass Through mode (see the TPT control bit in the T3/E3 Control Register).

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