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CAT9554WI-GT2 Datasheet(PDF) 2 Page - ON Semiconductor |
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CAT9554WI-GT2 Datasheet(HTML) 2 Page - ON Semiconductor |
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2 / 14 page ![]() CAT9554, CAT9554A http://onsemi.com 2 Figure 1. Block Diagram 8−BIT WRITE pulse READ pulse LP FILTER POWER−ON RESET INPUT FILTER CONTROL A0 A1 A2 SDA SCL INPUT/ OUTPUT PORTS INT VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I2C/SMBUS VCC VSS Note: All I/Os are set to inputs at RESET. Table 1. PIN DESCRIPTION SOIC / TSSOP TQFN Pin Name Function 1 15 A0 Address Input 0 2 16 A1 Address Input 1 3 1 A2 Address Input 2 4−7 2−5 I/O0−3 Input/Output Port 0 to Input/Output Port 3 8 6 VSS Ground 9−12 7−10 I/O4−7 Input/Output Port 4 to Input/Output Port 7 13 11 INT Interrupt Output (open drain) 14 12 SCL Serial Clock 15 13 SDA Serial Data 16 14 VCC Power Supply Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units VCC with Respect to Ground −0.5 to +6.5 V Voltage on Any Pin with Respect to Ground −0.5 to +5.5 V DC Current on I/O0 to I/O7 ±50 mA DC Input Current ±20 mA VCC Supply Current 85 mA VSS Supply Current 100 mA Package Power Dissipation Capability (TA = 25°C) 1.0 W Junction Temperature +150 °C Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units VZAP (Note 2) ESD Susceptibility JEDEC Standard JESD 22 2000 Volts ILTH (Notes 2, 3) Latch−up JEDEC Standard 17 100 mA 2. This parameter is tested initially and after a design or process change that affects the parameter. 3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V. |
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