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AX88875AP Datasheet(PDF) 5 Page - ASIX Electronics Corporation |
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AX88875AP Datasheet(HTML) 5 Page - ASIX Electronics Corporation |
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5 / 23 page  AX88875AP Bripeater ASIX ELECTRONICS CORPORATION 5 1.3 Block Diagram Fig - 1 Chip Block Diagram 10/100 Q-PHY 10/100 PHY or MAC MII I/F MII interface Re-concilia- tion Sub-layer (Port 0 - Port 4 ) Speed Detection circuit Elasticity Buffer for 100Mbps and 10Mbps MUX Repeater State Machine of 100Mbps Collision Handling Logic for 100Mbps and10Mbps Per port Jabber ctl, auto-partition SM & Per port Collision , Partition counters. Registers MIB I/F (Reserved) Cascade Arbitration Logic of 100Mbps (Reserved) MII I/F Repeater State Machine of 10Mbps 100Mbps to 10Mbps Bridge (Reserved) |
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