DSP56857 datasheet(215/662 Pages) FREESCALE

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Interrupts

Overview, Rev. 4

Freescale Semiconductor

8-37

this newly requested interrupt. The core will latch IPIC_LEVEL and it will be driven back to the

Interrupt Controller as new values on the SR_REG[9:8] pins.

When the 56800E core recognizes the assertion of the interrupt pin, it will deassert PIC_EN

which tells the Interrupt Controller to drive VAB with the address corresponding to the highest

priority interrupt request in order to start the interrupt service routine. When the 56800E core

asserts the IACK signal, the Interrupt Controller will deassert the interrupt signal to the core. The

controller will not reassert the interrupt signal until PIC_EN is asserted by the 56800E core.

Figure 8-26. Interrupt Handshake Timing

8.11.2 Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception

to be serviced. The following tables define the nesting requirements for each priority level.

Table 8-4. Interrupt Mask Bit Definition

Exceptions

Permitted

Exceptions

Masked

Priorities 0, 1, 2, 3

None

Priorities 1, 2, 3

Priority 0

Priorities 2,3

Priorities 0, 1

Priority 3

Priorities 0, 1, 2

VAB

CLK

INT

PIC_EN

SR_REG[9:8]

IACK

IPIC_LEVEL

IRQ_B

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