DSP56857 datasheet(262/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

5685X Digital Signal Controller User Manual, Rev. 4

10-26

Freescale Semiconductor

10.9.2.10 Transmitter Idle Interrupt Enable (TIIE)—Bit 6

This bit enables the Transmitter Idle (TIDLE) flag to generate interrupt requests.

•

0 = TIDLE interrupt requests disabled

•

1 = TIDLE interrupt requests enabled

10.9.2.11 Receiver Full Interrupt Enable (RFIE)—Bit 5

This bit enables the Receive Data Register Full (RDRF) flag, or the Overrun (OR) flag to

generate interrupt requests.

•

0 = RDRF and OR interrupt requests disabled

•

1 = RDRF and OR interrupt requests enabled

10.9.2.12 Receive Error Interrupt Enable (REIE)—Bit 4

This bit enables the Receive Error (RE) flags (NF, PF, FE, and OR) to generate interrupt

requests.

•

0 = Error interrupt requests disabled

•

1 = Error interrupt requests enabled

10.9.2.13 Transmitter Enable (TE)—Bit 3

This bit enables the SCI transmitter and configures the TXD pin as the SCI transmitter output.

The TE bit can be used to queue an idle preamble.

•

0 = Transmitter disabled

•

1 = Transmitter enabled

10.9.2.14 Receiver Enable (RE)—Bit 2

This bit enables the SCI Receiver.

•

0 = Receiver disabled

•

1 = Receiver enabled

10.9.2.15 Receiver Wake Up (RWU)—Bit 1

This bit enables the wake up function, inhibiting further receiver interrupt requests. Normally,

hardware wakes the receiver by automatically clearing the RWU. Please refer to Section 10.6.4.8

for a description of Receive Wake Up.

•

0 = Normal operation

•

1 = Standby state

DSP56857 Datasheet(PDF) 262 Page - Freescale Semiconductor, Inc

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