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DSP56857 Datasheet(PDF) 278 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 278 Page - Freescale Semiconductor, Inc

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Operating Modes
5685X Digital Signal Controller User Manual, Rev. 4
11-8
Freescale Semiconductor
Figure 11-3. Full-Duplex Master/Slave Connections
11.6.2 Slave Mode
The SPI operates in the Slave mode when the SPMSTR bit is clear. While in the Slave mode, the
SCLK pin is the input for the serial clock from the master DSC. Before a data transmission
occurs, the SS pin of the slave SPI must be at Logic 0. SS must remain low until the transmission
is complete or a Mode Fault Error occurs.
Note:
The SPI must be enabled (SPE = 1) for slave transmissions to be received.
Note:
Data in the Transmitter Shift register will be unaffected by SCLK transitions in the
event the SPI is operating as a slave but is deselected.
In a slave SPI module, data enters the Shift register under the control of the Serial Clock (SCLK)
from the Master SPI module. After a full length data transmission enters the Shift register of a
slave SPI, it transfers to the SPI Data Receive Register (SPDRR) and the SPI Receiver Full
(SPRF) bit in the SPI Status and Control Register (SPSCR) is set. If the Receive Data Register
(SPDRR), and the SPRF bit are set in the SPSCR, a receive interrupt is also generated. To
prevent an overflow condition, slave software must read the SPDRR before another full length
data transmission enters the Shift register.
The maximum frequency of the SCLK for a SPI configured as a slave is the bus clock speed. The
bus clock speed is twice as fast as the fastest master SCLK potential generation. Frequency of the
SCLK for an SPI configured as a slave does not have to correspond to any particular SPI baud
rate. The baud rate only controls the speed of the SCLK generated by an SPI configured as a
master. Therefore, the frequency of the SCLK for a SPI configured as a slave can be any
frequency less than, or equal to, the bus speed.
Shift Register
Shift Register
Baud Rate
Generator
Master DSC
Slave DSC
VDD
MOSI
MOSI
MISO
MISO
SCLK
SCLK
SS
SS



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