DSP56857 datasheet(282/662 Pages) FREESCALE

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Transmission Formats

5685X Digital Signal Controller User Manual, Rev. 4

11-12

Freescale Semiconductor

connected between the master and the slave. The MISO signal is the output from the slave, and

the MOSI signal is the output from the master.

The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when

its Slave Select input (SS) is at Logic 0 because only the selected slave drives to the master. The

SS pin of the master is not shown, but it is assumed to be inactive. While MODFEN = 1, the SS

pin of the master must be high or a Mode Fault Error will occur. If MODFEN = 0, the state of the

SS is ignored. When CPHA = 0, the first SCLK edge is the MSB capture strobe. Therefore, the

slave must begin driving its data before the first SCLK edge and a falling edge on the SS pin is

used to start the slave data transmission. The slave’s SS pin must be toggled back to high and

then low again between each full length data transmitted as depicted in Figure 11-7.

Note:

Figure 11-6 assumes 16-bit data lengths and the MSB shifted out first.

Figure 11-6. Transmission Format (CPHA = 0)

Figure 11-7. CPHA/SS Timing

When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission.

This causes the SPI to leave its idle state and begin driving the MISO pin with the first bit of its

data. Once the transmission begins, no new data is allowed into the Shift register from the SPI

Data Transmit Register (SPDTR). Therefore, the SPDTR of the slave must be loaded with

Bit 14

Bit 13

Bit 3

Bit 2

Bit 1

LSB

MSB

Bit 14

Bit 13

Bit 3

Bit 2

Bit 1

LSB

MSB

SCLK CYCLE #

(for Reference)

SCLK (CPOL = 0)

SCLK (CPOL =1)

MOSI

(from Master)

MISO

(from Slave)

SS (to Slave)

CAPTURE STROBE

........

Data 1

Data 3

MISO/MOSI

Data 2

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

DSP56857 Datasheet(PDF) 282 Page - Freescale Semiconductor, Inc

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