DSP56857 datasheet(286/662 Pages) FREESCALE

286 / 662 page

Transmission Data

5685X Digital Signal Controller User Manual, Rev. 4

11-16

Freescale Semiconductor

Figure 11-10. SPRF/SPTE Interrupt Timing

The transmit data buffer permits back-to-back transmissions without the slave precisely timing its

writes between transmissions as is necessary in a system with a single data buffer. Also, if no

new data is written to the data buffer, the last value contained in the Shift register is the next data

to be transmitted.

An idle master or idle slave without loaded data in its transmit buffer, sets the SPTE again no

more than two bus cycles after the transmit buffer empties into the Shift register. This allows a

queue to send up to a 32-bit value. For an already active slave, the load of the Shift register

Bit

MOSI

SCLK (CPHA:CPOL = 1:0)

SPTE

WRITE TO SPDTR

SPRF

READ SPSCR

MSB Bit

Bit

...

Bit

LSB MSB Bit

Bit

...

Bit

LSB

MSB Bit

Bit

...

DATA1

DATA2

DATA3

READ SPDRR

DSC WRITES DATA 1 TO SPDTR, CLEARING

THE SPTE BIT.

DATA 1TRANSFERS FROM TRANSMIT DATA

SPTE BIT.

DSC WRITES DATA 2 TO SPDTR, QUEUEING

DATA 2 AND CLEARING SPTE BIT.

FIRST INCOMING WORD TRANSFERS FROM

THE SHIFT REGISTER TO THE RECEIVE DATA

DATA 2 TRANSFERS FROM THE TRANSMIT

DATA REGISTER TO SHIFT REGISTER,

SETTING THE SPTE BIT.

DSC READS SPSCR WITH THE SPRF BIT SET.

DSC READS SPDRR, CLEARING SPRF BIT.

DSC WRITES DATA 3 TO SPDTR, QUEUEING

DATA 3 AND CLEARING THE SPTE BIT.

SECOND INCOMING DATA TRANSFERS FROM

SHIFT REGISTER TO RECEIVE DATA REGISTER

SETTING THE SPRF BIT.

DATA 3 TRANSFERSF ROM THE TRANSMIT DATA

THE SPTE BIT.

DSC READS SPSCR WITH THE SPRF BIT.

DSC READS SPDRR, CLEARING THE SPRF BIT.

DSP56857 Datasheet(PDF) 286 Page - Freescale Semiconductor, Inc

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