DSP56857 datasheet(287/662 Pages) FREESCALE

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Error Conditions

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-17

cannot occur until the transmission is completed. This implies a back-to- back write to the Data

Transmit Register (SPDTR) is not possible. The SPTE indicates when the next write can occur.

11.9 Error Conditions

The following flags signal SPI error conditions:

•

Overflow (OVRF) — Failing to read the SPI Data Register before the next full length data

enters the Shift register sets the OVRF bit. The new data will not transfer to the Data

Receive Register (SPDRR), and the unread data can still be read. OVRF is in the SPI

Status and Control Register (SPSCR).

•

Mode Fault Error (MODF) — The MODF bit indicates the voltage on the Slave Select pin

(SS) is inconsistent with the mode of the SPI. MODF is in the SPSCR.

11.9.1 Overflow Error

The Overflow Flag (OVRF) becomes set if the Data Receive Register (SPDRR) still has unread

data from a previous transmission and when bit one’s capture strobe of the next transmission

occurs. Bit 1 capture strobe occurs in the middle of SCLK when the Data Length = Transmission

Data Length - 1. If an overflow occurs, all data received after the overflow, and before the OVRF

bit is cleared, does not transfer to the SPDRR. It does not set the SPI Receiver Full (SPRF) bit.

The unread data transferred to the SPDRR before the overflow occurred can still be read.

Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading

the SPI Status and Control Register (SPSCR), then read the SPI Data register.

OVRF generates a receiver/error interrupt request if the Error Interrupt Enable (ERRIE) bit is

also set. It is not possible to enable MODF or OVRF individually in order to generate a

receiver/error interrupt request. However, leaving MODFEN low prevents MODF from being

set.

If the SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.

Figure 11-11 explains how it is possible to miss an overflow. The first element of the same figure

illustrates how it is possible to read the SPSCR and SPDRR to clear the SPRF without problems.

However, as illustrated by the second transmission example, the OVRF bit can be set between the

time SPSCR and SPDRR are read.

DSP56857 Datasheet(PDF) 287 Page - Freescale Semiconductor, Inc