DSP56857 datasheet(283/662 Pages) FREESCALE

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Transmission Formats

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-13

transmit data before the falling edge of SS. Any data written after the falling edge is stored in the

SPDTR and transferred to the Shift register after the current transmission.

When CPHA = 0 for a master, normal operation would begin by the master initializing the SS pin

of the slave high. A transfer would then begin by the master setting the SS pin of the slave low and

then writing the SPDTR. After completion of a data transfer, the SS pin would be put back into

the high state by the master device.

11.7.5 Transmission Format When CPHA = 1

A SPI transmission is shown in Figure 11-8 where CPHA is Logic1. The figure should not be

used as a replacement for data sheet parametric information. Two waveforms are shown for

SCLK: 1 for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or

slave timing diagram since the serial clock (SCLK), Master In/Slave Out (MISO), and Master

Out/Slave In (MOSI) pins are directly connected between the master and the slave. The MISO

signal is the output from the slave, and the MOSI signal is the output from the master. The SS

line is the Slave Select input to the slave. The slave SPI drives its MISO output only when its

Slave Select input (SS) is at Logic 0, so only the selected slave drives to the master. The SS pin of

the master is not shown but is assumed to be inactive. The SS pin of the master must be high or a

Mode Fault Error occurs. When CPHA = 1, the master begins driving its MOSI pin on the first

SCLK edge. Therefore, the slave uses the first SCLK edge as a start transmission signal. The SS

pin can remain low between transmissions. This format may be preferable in systems having only

one master and slave driving the MISO data line.

Note:

Figure 11-8 assumes 16-bit data lengths and the MSB shifted out first.

Figure 11-8. Transmission Format (CPHA = 1)

Bit 14

Bit 13

Bit 3

Bit 2

Bit 1

LSB

MSB

Bit 14

Bit 13

Bit 3

Bit 2

Bit 1

LSB

MSB

SCLK CYCLE #

(for Reference)

SCLK (CPOL = 0)

SCLK (CPOL =1)

MOSI

(from Master)

MISO

(from Slave)

SS (to Slave)

CAPTURE STROBE

........

DSP56857 Datasheet(PDF) 283 Page - Freescale Semiconductor, Inc

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