DSP56857 datasheet(290/662 Pages) FREESCALE

290 / 662 page

Error Conditions

5685X Digital Signal Controller User Manual, Rev. 4

11-20

Freescale Semiconductor

In a Master SPI with the Mode Fault Enable (MODFEN) bit set, the Mode Fault (MODF) flag is

set if SS goes to Logic 0. A Mode Fault in a Master SPI causes the following events to occur:

•

If ERRIE = 1, the SPI generates a SPI receiver/error interrupt request

•

The SPE bit is cleared (SPI disabled)

•

The SPTE bit is set

•

The SPI state counter is cleared

When configured as a slave (SPMSTR = 0), the MODF flag is set if the SS goes high during a

transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the

incoming SCLK goes back to its idle level, following the shift of the last data bit. When CPHA =

1, the transmission begins when the SCLK leaves its idle level and SS is already low. The

transmission continues until the SCLK returns to its idle level following the shift of the last data

bit.

Note:

Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no

function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference

between a MODF occurring when the SPI is a master and when it is a slave.

When CPHA = 0, a MODF occurs if a slave is selected (SS is at Logic 0) and later

unselected (SS is at Logic 1) even if no SCLK is sent to that slave. This happens

because SS at Logic 0 indicates the start of the transmission (MISO driven out with

the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then

later unselected with no transmission occurring. Therefore, MODF does not occur

since a transmission was never begun.

In a Slave SPI (MSTR = 0), the MODF bit generates a SPI Receiver/Error Interrupt request if the

ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software

can abort the SPI transmission by clearing the SPE bit of the slave.

Note:

A logic one voltage on the SS pin of a slave SPI puts the MISO pin in a high

impedance state. Also, the slave SPI ignores all incoming SCLK clocks, even if it was

already in the middle of a transmission.

In a master SPI, the MODF flag will not be cleared until the SS pin is at a Logic 1 or the SPI is

configured as a slave.

In a slave SPI, if the MODF flag is not cleared by writing 1 to the MODF bit, the condition causing

the Mode Fault still exists. The MODF flag and corresponding interrupt can be cleared by

disabling the EERIE or MODFEN bits (if set) or by disabling the SPI. It is possible to clear the

MODF error condition by disabling the SPE or MODFEN bits. Disabling the SPI using the SPE

bit will cause a partial reset of the SPI and may cause the loss of a message currently being

received or transmitted.

DSP56857 Datasheet(PDF) 290 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 290 Page - Freescale Semiconductor, Inc

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