DSP56857 datasheet(294/662 Pages) FREESCALE

294 / 662 page

SPI Register Descriptions (SPI_BASE = $1FFFE8)

5685X Digital Signal Controller User Manual, Rev. 4

11-24

Freescale Semiconductor

The Mode Fault Enable (MODFEN) bit can retard the MODF flag from being set. The retarded

bit results in only the OVRF bit being enabled by the ERRIE bit. This enabling generates

Receiver/Error Interrupt requests.

11.11.1.5 SPI Receiver Interrupt Enable (SPRIE)—Bit 9

This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set

when a full data length transfers from the Shift register to the SPI Data Receive Register (). The

SPI Receiver Interrupt Enable (SPRIE) bit enables the SPRF bit to generate receiver interrupt

requests regardless of the state of the SPE bit. The clearing mechanism for the SPRF flag is

always just a read to the SPDRR.

•

0 = SPRF interrupt requests disabled

•

1 = SPRF interrupt requests enabled

11.11.1.6 SPI Master (SPMSTR)—Bit 8

This read/write bit selects master mode operation or slave mode operation.

•

0 = Slave mode

•

1 = Master mode (default)

11.11.1.7 Clock Polarity (CPOL)—Bit 7

This read/write bit determines the logic state of the SCLK pin between transmissions. To transmit

data between SPI modules, the SPI modules must have identical CPOL values.

•

0 = Falling edge of SCLK starts transmission

•

1 = Rising edge of SCLK starts transmission

11.11.1.8 Clock Phase (CPHA)—Bit 6

This read/write bit controls the timing relationship between the serial clock and SPI data. To

transmit data between SPI modules, the SPI modules must have identical CPHA

values. When CPHA = 0, the SS pin of the slave SPI module must be set to Logic 1 between full

length data transmissions. Do not use CPHA = 0 while in the DMA mode.

11.11.1.9 SPI Enable (SPE)—Bit 5

This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. When

setting/clearing this bit, no other bits in the SPSCR should be changed. Failure to following this

statement may result in spurious clocks.

•

0 = SPI module disabled

•

1 = SPI module enabled.

DSP56857 Datasheet(PDF) 294 Page - Freescale Semiconductor, Inc

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