DSP56857 datasheet(296/662 Pages) FREESCALE

296 / 662 page

SPI Register Descriptions (SPI_BASE = $1FFFE8)

5685X Digital Signal Controller User Manual, Rev. 4

11-26

Freescale Semiconductor

11.11.1.14 SPI Transmitter Empty (SPTE)—Bit 0

This read-only flag is set each time the SP Data Transmit Register (SPDTR) transfers a full data

length into the Shift register. SPTE generates an interrupt request if the SPTIE bit in the SPI Sta-

tus and Control Register (SPSCR) is set also. This bit may be cleared using the proper software

sequence.

•

0 = Data Transmit register not empty

•

1 = Data Transmit register empty

Note:

Do not write to the SPI Data Register unless the SPTE bit is high.

11.11.2 SPI Data Size and Control Register (SPDSCR)

This read/write register determines the data length for each transmission. The master and slave

must transfer the same size data on each transmission. A new value will only take effect at the

time the SPI is enabled (SPE bit in SPSCR register set from zero to one). In order to have a new

value take effect, disable then re-enable the SPI with the new value in the register. The SPDSCR:

•

Enables SPI DMA mode for the Transmitter and Receiver

•

Enables Wired OR mode on MISO and MOSI

•

Configures the size of the transmission

Figure 11-15. SPI Data Size and Control Register (SPDSCR)

See Programmer’s Sheets on Appendix page B-65

11.11.2.1 Wired OR Mode (WOM)—Bit 15

This control bit is used to select the nature of the SPI pins. When enabled, the WOM bit is set, the

SPI pins are configured as open-drain drivers with the pull-ups disabled. However, when

disabled, the WOM bit is cleared, and the SPI pins are configured as push-pull drivers.

•

0 = Wired OR mode disabled

•

1 = Wired OR mode enabled

11.11.2.2 Transmitter DMA Enable (TDMAEN)—Bit 14

In the DMA mode, normal interrupts (not error) are suppressed and a DMA Request is generated

instead. The requirement for clearing SPRF/SPTE changes to read/write the SPDRR/SPDTR,

thereby eliminating the read of SPSCR.

Base +$1

Read

WOM TDMAEN RDMAEN

TDS

Write

Reset

000000000

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