DSP56857 datasheet(314/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

12-14

Freescale Semiconductor

12.5.2 Network Mode

Network mode is used for creating a Time Division Multiplexed (TDM) network, such as a TDM

codec network or a network of DSCs. This mode only operates with continuous clock mode. A

frame sync occurs at the beginning of each frame. In this mode, the frame is divided into more

than one time slot. During each time slot, one data word can be transferred. Each time slot is then

assigned to an appropriate codec or DSC on the network. The DSC can be a master device

controlling its own private network, or a slave device connected to an existing TDM network,

occupying a few time slots.

The frame sync signal indicates the beginning of a new data frame. Each data frame is divided

into time slots and transmission and/or reception of one data word can occur in each time slot

(rather than in just the frame sync time slot as in the Normal mode). The frame rate dividers,

controlled by the DC bit field, select two to thirty-two time slots per frame. The length of the

frame is determined by these factors:

•

The period of the serial bit clock (PSR, PM[7:0] bits for internal clock, or the frequency of

the external clock on the SCK and/or SC0 pins)

•

The number of bits per sample (WL) bits

•

The number of time slots per frame (DC) bit fields

Data can be transmitted in any time slot while in the Network mode. The distinction of the

Network mode is each time slot is identified with respect to the frame sync (data word time). This

time slot identification allows the option of transmitting data during the time slot by writing to

the STX register or ignoring the time slot by writing to STSR. The receiver is treated in the same

manner, except data is always being shifted into the RXSR and transferred to the SRX register.

The core reads the SRX register, either using the data or discarding it.

Figure 12-4 and Figure 12-5 provide sample timing of Network mode transfers. The figures

illustrate Receive and Transmit frames of five time-slots for each. The numbered circles and

arrows in the figure identify discussion notes contained in Table 12-8 and Table 12-9.

12.5.2.1 Network Mode Transmit

The transmit portion of the ESSI is enabled when the ESSIEN and the TE bits in the SCR2 are

both set. However, when the TE bit is set, the transmitter is enabled only after detection of a new

frame boundary. Software has to find the start of the next frame by checking the TFS bit of the

SSR. A normal start-up sequence for transmission is to do the following:

1. Set the STXCR, SCR2, SCR3, and SCR4 registers to select the Network mode operation.

2. Define the transmit clock.

3. Transmit frame sync and frame structure required for proper system operation.

DSP56857 Datasheet(PDF) 314 Page - Freescale Semiconductor, Inc