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DSP56857 Datasheet(PDF) 315 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 315 Page - Freescale Semiconductor, Inc |
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315 / 662 page  Functional Description Enhanced Synchronous Serial Interface (ESSI), Rev. 4 Freescale Semiconductor 12-15 4. ESSI enabled (ESSIEN = 1) 5. Enable TXFIFO (TFEN = 1) and configure the Transmit Watermark (TFWM = n) if this TXFIFO is used. 6. Write data to transmit data register (STX). 7. Enable transmit interrupts. 8. Set the TE bit (TE = 1) to enable the transmitter on the next frame sync boundary. The transmitter timing for an 8-bit word with continuous clock, FIFO disabled, five words per frame sync, in the Network mode is shown in Figure 12-4. The explanatory notes for the transmit portion of the figure are provided in Table 12-8. Figure 12-4. Network Mode Transmit Timing TS 0 TS 1 TS 2 TS 3 TS 4 TS 0 Time Slot SCK Internal Word Clock SC2 TFS Bit of SSR Register TDE Status Bit / Interrupt STX Register STSR Register TXSR Register STD 2 4 5 1 3 4 Valid Indefinite transition depends on SW interrupt processing Invalid |
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