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DSP56857 Datasheet(PDF) 319 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 319 Page - Freescale Semiconductor, Inc

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Functional Description
Enhanced Synchronous Serial Interface (ESSI), Rev. 4
Freescale Semiconductor
12-19
shown in Figure 12-6. If it is desired to run off a single set of interrupts, the TX interrupts should
be used. If RX interrupts are used, there may be timing problems with the transmit data because
this interrupt occurs a half-bit time before the transmit data is used by the hardware.
Figure 12-6. Synchronous Mode Interrupt Timing
12.5.4 Network Mode with Mask Registers Implemented
In order to reduce interrupt overhead, a number of enhancements were made to the ESSI module.
The enhancements incorporate the mask registers (TSM and RSM).
Together, Figure 12-8 and Figure 12-33 illustrate sample timing of Network mode transfers
using the mask registers. These figures duplicate the frame structure of Figure 12-5 to illustrate
the reduced amount of interrupt processing required. The numbered circles and arrows in the
figures identify discussion notes contained in Table 12-10 and Table 12-11.
12.5.4.1 Operation Using TSM Register
When the TSM register is included in the design interrupt overhead can be reduced. If all bits of
the TSM register are set, the ESSI transmitter will continue to operate as previously described.
The TSM register is used to disable the STD pin on specific time-slots. This is accomplished by
writing the TSM with 0 in the time-slot bit location. Disabling a time- slot in this manner causes
the time-slot to be ignored by the ESSI. This means no data is transferred to the Transmit Shift
Register (TXSR), therefore interrupts are not generated for this time-slot. The transmitter timing,
using TSM registers for an 8-bit word, continuous clock with disabled FIFO five words per frame
sync in the Network mode is illustrated in Figure 12-7. Explanatory notes for the transmit
portion of the figure are provided in Table 12-10.
SCK
SC2
STX Register
TDE Status Bit / Interrupt
RDR Status Bit / Interrupt
Valid
Indefinite transition depends on SW interrupt processing
Invalid
TX Interrupt
RX Interrupt
TX Interrupt
RX Interrupt



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