DSP56857 datasheet(321/662 Pages) FREESCALE

321 / 662 page

Functional Description

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-21

12.5.4.2 Operation Using RSM Register

When the RSM register is included in the design, interrupt overhead can be reduced. If all bits of

the RSM register are set, the ESSI receiver will continue to operate as previously described. The

RSM register is used to automatically discard data from selected time slots. This is accomplished

by writing the RSM with 0 in the selected time-slot bit location. This means no data is transferred

from the Receive Data Shift Register (RXSR) on the zero time-slots, no status flags change, and

no interrupts are generated.

Receiver timing in the Network mode, and using RSM registers for an 8-bit word with a

continuous clock, results in the disabled FIFO five words per frame sync. In this example there

are only two receive interrupts per frame instead of five as in the previous example where the

RSM register is not used. This process is illustrated in Figure 12-8 and explained in Table 12-11.

Table 12-10.

Notes for Transmit Timing with Mask Register in Figure 12-8

Note

Source

Signal

Destination

Signal

Description

—

Example of a five time slot frame, transmitting in time slots 0 and 3.

2SC2

—

Example of a word length frame sync and standard timing (TFSI=0, TFSL=0,

and TEFS=0). Frame timing begins with the rising edge of SC2.

3—

TDE Status Flag

and Interrupt

For enabled time slots, this flag is set at the beginning of each word to

indicate the STX data has been used and another data word should be

supplied by the software. If the transmit interrupt is enabled the processor is

interrupted to request the data. The flag and interrupt are cleared when data

is written to either the STX or STSR registers.1

STX / STSR

TXSR

On each word clock boundary a decision is made concerning what to

transmit on the next time slot. If the TSMn register bit is zero for the next

time slot, the STD pin is tri-stated and the time slot is ignored.

When the TSMn bit is one for the next time slot, the contents or the STX

the STX register has not been written in the previous time slot, the previous

data is reused.

Note:

If the STSR is written instead of the STX, the STD pin is

tri-stated as stated in Section 12.5.2.1.

When neither of these registers were written in the previous time slot (where

TSMn=1), the TUE status bit will be set and the hardware will operate as if

the STX register had been written. The STD pin will be enabled and the

contents of the STX will be transmitted again. This may lead to drive conflicts

on the transmit data line, in another device is transmitting data during this

time slot.

TXSR

STD Pin

On active time slots, the TXSR register contents are shifted out on the STC

pin, one bit per rising edge of SCK.

On inactive time slots, the STD pin is tri-stated so it can be driven by another

device.

Section 12.13 provides a complete description of the interrupt process.

DSP56857 Datasheet(PDF) 321 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 321 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL