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DSP56857 Datasheet(PDF) 325 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 325 Page - Freescale Semiconductor, Inc |
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325 / 662 page  Module Memory Map Enhanced Synchronous Serial Interface (ESSI), Rev. 4 Freescale Semiconductor 12-25 12.7 Module Memory Map Nine registers make up the ESSI peripheral and are summarized in Table 12-12 and Figure 12-11. Table 12-12. ESSI Module Memory Map (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00) Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 STX0 Transmit Data Register 0 Write-Only Section 12.8.1 Base + $1 STX1 Transmit Data Register 1 Write-Only Section 12.8.2 Base + $2 STX2 Transmit Data Register 2 Write-Only Section 12.8.3 Base + $3 SRX Receive Data Register Read-Only Section 12.8.4 Base + $4 SSR Status Register Read-Only Section 12.8.7 Base + $5 SCR2 Control Register 2 Read/Write Section 12.8.8 Base + $6 SCR3 Control Register 3 Read/Write Section 12.8.9 Base + $7 SCR4 Control Register 4 Read/Write Section 12.8.10 Base + $8 STXCR Transmit Control Register Read/Write Section 12.8.11 Base + $9 SRXCR Receive Control Register Read/Write Base + $A STSR Time Slot Register Write-Only Section 12.8.12 Base + $B SFCSR FIFO Control/Status Register Read-Only Section 12.8.13 Base + $C TSMA Transmit Slot Mask Register Read/Write Section 12.8.14 Base + $D TSMB Transmit Slot Mask Register Read/Write Base + $E RSMA Receive Slot Mask Register Read/Write Section 12.8.15 Base + $F RSMB Receive Slot Mask Register Read/Write Add. Offset Register Name 15 14 13 12 11 10 98765 4321 0 $0 STX0 R WDATA $1 STX1 R WDATA $2 STX2 R WDATA $3 SRX R HIGH BYTE LOW BYTE W $4 SSR RIF1 IF0 TFF TLS RLS TF1ERR TF2ERR RDR TDE ROE TUE TFS RFS RFF TFE W $5 SCR2 R RIE TIE RE TE0 TE1 TE2 SYN TSHFD TSCKP ESSIEN NET TFSI TFSL TEFS W $6 SCR3 R DIV4DIS RSHFD RSCKP RD MAE TD MAE RFSI RFSL REFS RFEN TFEN INIT SYNRST RLIE TLIE W $7 SCR4 R TXSF0 TXSF1 TXSF2 SSC1 SCKD SCD2 SCD1 SCD0 OF1 OF0 W Figure 12-11. ESSI Register Map Summary |
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