DSP56857 datasheet(327/662 Pages) FREESCALE

327 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-27

Note:

Enable ESSI (ESSIEN = 1), before writing to Transmit Data Register and Transmit

FIFO.

Figure 12-12. ESSI Transmit Data Register 0 (STX0)

See Programmer’s Sheet on Appendix page B - 68

Figure 12-13. ESSI Transmit Data Register 1 (STX1)

See Programmer’s Sheet on Appendix page B - 68

Figure 12-14. ESSI Transmit Data Register 2 (STX2)

See Programmer’s Sheet on Appendix page B - 68

12.8.2 ESSI Transmit FIFO Registers (TXFIFO0, TXFIFO1, TXFIFO2)

The 8

× 16-bit TXFIFO registers are used to buffer samples written to the Transmit Data

Registers (STX0-2). They are written by the contents of the Transmit Data Registers (STX0-2)

whenever the transmit FIFO feature is enabled. If enabled, the Transmit Shift Registers

(TXSR0-2) receive their values from the FIFO registers. If the transmit FIFO feature is not

enabled, this register is bypassed and the contents of STX0-2 registers are transferred into the

Transmit Shift Registers (TXSR0-2).

When the Transmit Interrupt Enable (TIE) bit in the SCR2 and Transmit Data Register Empty

(TDE) bit in the SSR are set, the transmit interrupt is asserted whenever STX0-2 are empty and

the data level in the ESSI transmit FIFO falls below the selected threshold.

Base + $0

Read

Write

DATA

Reset

Base + $1

Read

Write

DATA

Reset

Base + $2

Read

Write

DATA

Reset

DSP56857 Datasheet(PDF) 327 Page - Freescale Semiconductor, Inc