DSP56857 datasheet(331/662 Pages) FREESCALE

331 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-31

12.8.7 ESSI Status Register (SSR)

This is a 16-bit, read-only register except for the RLS and TLS bits described in the following

third note. It is used to monitor the ESSI. The register is used to interrogate the status and serial

input flags of the ESSI. The status bits are described in the following paragraphs.

Figure 12-20. ESSI Status Register (SSR)

See Programmer’s Sheet on Appendix page B - 70

Note:

ESSI Status flag is updated when the ESSI is enabled.

Note:

All flags in the status portion of the SSR are updated after the first bit of the next ESSI

word has completed transmission or reception. The ROE and TUE status bits are

cleared by reading the SSR followed by a read/write to either the SRX or STX0-2

Note:

The RLS and TLS status bits are cleared by reading the SSR, then writing 1 to the

appropriate bit of the SSR.

12.8.7.1 Input Flag 1 (IF1)—Bit 15

The IF1 bit is enabled only when SC1 is configured as an input flag and the Synchronous mode is

selected. For example, when the SYN bit is set and the TE2 and SCD1 bits are cleared. Please

refer to Table 12-15.

The ESSI latches any data present on the SC1 signal during reception of the first received bit

after the frame sync is detected. The IF1 bit is updated with this data when the data in the Receive

Shift Register is transferred into the Receive Data Register

If it is not enabled, the IF1 bit is cleared.

12.8.7.2 Input Flag 0 (IF0)—Bit 14

The IF0 bit is enabled only when SC0 is configured as an input flag and the Synchronous mode is

selected; that is to say, when the SYN bit is set and the TE1 and SCD0 bits are cleared. Please see

Table 12-16 for more information.

The ESSI latches any data present on the SC0 signal during reception of the first received bit

after the frame sync is detected. The IF0 bit is updated with this data when the data in the Receive

Base + $4

Read

IF1

IF0

TFF

TLS

RLS

TF1ERR

TF2ERR RDR TDE ROE TUE

TFS

RFS

RFF

TFE

Write

Reset

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