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DSP56857 Datasheet(PDF) 335 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 335 Page - Freescale Semiconductor, Inc |
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335 / 662 page  Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00) Enhanced Synchronous Serial Interface (ESSI), Rev. 4 Freescale Semiconductor 12-35 12.8.7.13 Transmit Frame Sync (TFS)—Bit 3 The middle section of Figure 12-21exhibits data written to the STX Register in the Network mode during the time slot when the TFS bit is set. This is transmitted during either of the following: • Second time slot (in the Network mode) • In the following first time slot (in the Normal mode) While in Network mode, the TFS bit is set during transmission of the first slot of the frame. The bit is then cleared when starting transmission of the next slot. The TFS bit is cleared by Power-On Reset (POR) or ESSI reset (ESSIEN = 0). 12.8.7.14 Receive Frame Sync (RFS)—Bit 2 When set, this flag bit indicates a frame sync occurred during receiving of the next word into the SRX Register. The process is illustrated in the lower portion of Figure 12-21. In the Network mode, the RFS bit is set while the first slot of the frame is being received. It is cleared when the next slot of the frame begins to be received. The RFS bit is cleared by Power-On Reset (POR) or ESSI reset (ESSIEN = 0). |
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