DSP56857 datasheet(338/662 Pages) FREESCALE

338 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-38

Freescale Semiconductor

12.8.8.1 Receive Interrupt Enable (RIE)—Bit 15

This control bit allows interrupting the program controller. When the RIE and RE bits are set, the

program controller is interrupted when the ESSI receives data. As provided in Table 12-13, the

interrupt trigger depends on whether the receive FIFO is enabled.

If the receive FIFO is disabled:

•

0 = No interrupt is generated.

•

1 = An interrupt is generated when the RDR flag in the SSR is set. One value can be read

from the SRX register. Reading the SRX register clears the RDR bit, thus clearing the

interrupt.

If the receive FIFO is enabled:

•

0 = No interrupt is generated.

•

1 = An interrupt is generated when the RFF flag in the SSR is set. A maximum of eight

values are available to be read from the SRX register. To clear the RFF bit interrupt, read

the SRX register, removing data from the Receive FIFO, thereby dropping the data level

below the watermark.

Two receive data interrupts with separate interrupt vectors are available:

1. Receive data with exception status.

2. Receive data without exception.

Generated interrupt vectors and their conditions are listed in Table 12-13.

12.8.8.2 Transmit Interrupt Enable (TIE)—Bit 14

This control bit provides program controller interruption. When the TIE and TE0-2 bits are set

the program controller is interrupted when the ESSI needs more transmit data lists. The interrupt

trigger depends whether the transmit FIFOs are enabled, shown in Table 12-14.

Table 12-13. ESSI Receive Data Interrupts 1

Table 12-27 provides a complete list of interrupts.

Interrupt

RIE

Selection Control

ROE

RFEN = 0

RFEN = 1

Receive Data with Exception Status

RDR = 1

RFF = 1

Transmit Date without Exception Status

RDR = 1

RFF = 1

DSP56857 Datasheet(PDF) 338 Page - Freescale Semiconductor, Inc

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