DSP56857 datasheet(340/662 Pages) FREESCALE

340 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-40

Freescale Semiconductor

12.8.8.5 Transmit Enable 0 (TE0)—Bit 12

This control bit enables the transfer of the contents of the STX0 register to its Transmit Data Shift

modes.

•

0 = The transmitter continues to send the data currently in TXSR0, then disables the

transmitter.

•

1 = On the next frame boundary, the transmit 0 portion of the ESSI is enabled. With

internally generated clocks, the frame boundary will occur within a word time. If the TE0

bit is cleared, then set again during the same transmitted word, the data continues to be

transmitted. If the TE0 bit is set again during a different time slot, data is not transmitted

until the next frame boundary.

The serial output is tri-stated and any data present in the STX0 register is not transmitted. For

example, data can be written to the STX0 register with the TE0 bit cleared and the TDE bit is

cleared, but data is not transferred to the TXSR0.

The Normal Transmit Enable sequence is to write data to the STX0 register or to the STSR

before setting the TE0 bit. The Normal Transmit Disable sequence is to clear both the TE0 and

TIE bits after the TDE bit is set. This bit should be cleared when clearing ESSIEN.

12.8.8.6 Transmit Enable 1 (TE1)—Bit 11

This control bit enables the transfer of the contents of the STX1 register to its Transmit Data Shift

when the ESSI is in the Asynchronous mode.

•

0 = The transmitter continues to send the data currently in TXSR1, then disables the

transmitter. The serial output is tri-stated and any data present in the STX1 register is not

transmitted. In other words, data can be written to the STX1 register with the TE1 bit

cleared and the TDE bit is cleared but data is not transferred to the TXSR1.

•

1 = On the next frame boundary, the Transmit 1 portion of the ESSI is enabled for that

frame. With internally generated clocks, the frame boundary will occur within a word

time. If the TE1 bit is cleared and then set again during the same transmitted word, the

data continues to be transmitted. If the TE1 bit is set again during a different time slot,

data is not transmitted until the next frame boundary.

When the TE1 bit remains clear until the beginning of the next frame, it causes the SC0 signal to

act as a serial I/O flag from the start of the frame in both Normal and Network modes.

The Normal Transmit Enable sequence is to write data to the STX1 register or to the STSR

before setting the TE1 bit. The Normal Transmit Disable sequence is to clear the TE1 and TIE

bits after the TDE bit is set. This bit should be cleared when clearing ESSIEN.

Note:

Setting the TE1 bit does not affect the generation of frame sync or output flags.

DSP56857 Datasheet(PDF) 340 Page - Freescale Semiconductor, Inc

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