DSP56857 datasheet(343/662 Pages) FREESCALE

343 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-43

12.8.8.15 Transmit Frame Sync Length (TFSL)—Bit 1

This control bit selects the length of the frame sync signal to be generated or recognized. See the

upper portion of Figure 12-21 for an example timing diagram of the frame sync options.

•

0 = A one-word long frame sync is selected. The length of this word-long frame sync is

the same as the length of the data word selected by WL.

•

1 = A one-bit long frame sync is selected

The frame sync is deasserted after one bit-for-bit length frame sync and after one word- for-word

length frame sync.

12.8.8.16 Transmit Early Frame Sync (TEFS)—Bit 0

This bit controls when the frame sync is initiated for the transmit and receive sections. Please

refer to the upper portion of Figure 12-21 for a timing diagram example of the frame sync

options.

•

0 = Frame sync is initiated as the first bit of data is transmitted.

•

1 = Frame sync is initiated one-bit before the data is transmitted. The frame sync is

disabled after one bit-for-bit length frame sync and after one word-for-word length frame

sync.

12.8.9 ESSI Control Register 3 (SCR3)

The ESSI Control Register 3 (SCR3) is one of five 16-bit, read/write control registers used to

direct the operation of the ESSI. SCR3 controls enabling of the last slot interrupts for Network

mode transmit and receive operations.

The Power-On Reset (POR) clears all SCR3 bits. The ESSI reset (ESSIEN = 0) does not affect

the SCR3 bits.

Figure 12-23. ESSI Control Register 3 (SCR3)

See Programmer’s Sheet on Appendix page B - 75

Base + $6

Read

DIV4DIS RSHFD RSCKP RDMAE TDMAE

RFSI RFSL REFS RFEN TFEN INIT

SYNRST

RLIE TLIE

Write

Reset

DSP56857 Datasheet(PDF) 343 Page - Freescale Semiconductor, Inc