DSP56857 datasheet(346/662 Pages) FREESCALE

346 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-46

Freescale Semiconductor

12.8.9.8 Receive Early Frame Sync (REFS)—Bit 8

This bit controls when the frame sync is initiated for the receive section. Please note the first

portion of Figure 12-21 for an example timing diagram of the frame sync options.

•

0 = When the REFS bit is cleared, the frame sync is initiated as the first bit of data is

received.

•

1 = The frame sync is initiated one-bit before the data is received. The frame sync is

disabled after one bit-for-bit length frame sync and after one word-for-word length frame

sync.

12.8.9.9 Receive FIFO Enable (RFEN)—Bit 7

This control bit enables the FIFO register for the receive section.

•

0 = The FIFO register is not used, and an interrupt request is generated (assuming

interrupts are enabled) when a single sample is received by the ESSI and RDR is set.

•

1 = Allows eight samples, depending on the Receive Watermark set in the SFCSR, to be

received by the ESSI. A ninth sample can be shifting in before the RFF bit is set and an

interrupt request generated when enabled by the RIE bit.

12.8.9.10 Transmit FIFO Enable (TFEN)—Bit 6

This control bit enables the FIFO registers for the transmit section.

•

0 = The FIFO register is not used.

•

1 = A maximum of eight samples can be written to the STX register. A ninth sample can

be shifting out.

12.8.9.11 Initialize State Machine (INIT)—Bit 5

This bit is used to initialize the state machine to reset state.

•

0 = The state machine is allowed to operate.

•

1 = Reset the TX and RX state machines. Setting this bit must be followed by a write of 0

before the state machine will operate.

12.8.9.12 Reserved—Bit 4–3

These bits are reserved or not implemented. They cannot be read or modified by writing.

12.8.9.13 Frame Sync Reset (SYNRST)—Bit 2

•

0 = Data must be read to be cleared from the registers.

•

1 = Resets the accumulation of data in the SRX register and RXFIFO bit in frame

synchronization.

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