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DSP56857 Datasheet(PDF) 347 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 347 Page - Freescale Semiconductor, Inc

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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
Enhanced Synchronous Serial Interface (ESSI), Rev. 4
Freescale Semiconductor
12-47
12.8.9.14 Receive Last Slot Interrupt Enable (RLIE)—Bit 1
•
0 = The Receive Last Slot Interrupt is disabled.
•
1 = An interrupt is generated after the last slot of a receive frame ends when the ESSI is in
the Network mode. The interrupt occurs regardless of the receive mask register setting.
Note:
The RLIE bit is disabled when DC = 00.
12.8.9.15 Transmit Last Slot Interrupt Enable (TLIE)—Bit 0
•
0 = The Transmit last slot interrupt is disabled.
•
1 = An interrupt is generated at the beginning of the last slot of a transmit frame when the
ESSI is in the Network mode. The interrupt occurs regardless of the transmit mask register
setting.
Note:
The TLIE bit is disabled when DC = 00.
12.8.10 ESSI Control Register 4 (SCR4)
The ESSI Control Register 4 (SCR4) is one of five, 16-bit, read/write control registers used to
direct the operation of the ESSI. The SCR4 controls the configuration of the ESSI I/O pins and
specifies the values of the Output Flag controls.
The Power-On Reset (POR) clears all of the SCR4 bits. The ESSI reset (ESSIEN = 0) does not
affect the SCR4 bits. The SCR4 bits are discussed in the following paragraphs.
Figure 12-24. ESSI Control Register 4 (SCR4)
See Programmer’s Sheet on Appendix page B - 76
12.8.10.1 Reserved—Bits 15–11
These bits are reserved or not implemented. They cannot be read nor modified by writing.
12.8.10.2 Transmit Status Flag Control 0 (TXSF0)—Bit 10
•
0 = The indicated transmitter does not affect the status bits.
•
1 = The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits.
The status from all selected transmitters is ORed to create the register status bit. These bits
should be set to match the intended operation of the TE0, TE1, and TE2 control bits.
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TXSF0 TXSF1 TXSF2
0
SSC1 SCKD SCD2 SCD1
SCD0
OF1
OF0
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0



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