DSP56857 datasheet(344/662 Pages) FREESCALE

344 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-44

Freescale Semiconductor

12.8.9.1 Divider 4 Disable (DIV4DIS)—Bit 15

•

0 = FIX_CLK = IP_CLK/4 for both transmitter and receiver clock generator circuits

•

1 = FIX_CLK is equal to IP_CLK

12.8.9.2 Receive Shift Direction (RSHFD)—Bit 14

This bit controls whether the MSB or LSB is received first for the receive section.

•

0 = Data is received MSB first

•

1 = Data is received LSB first

Note:

The codec device labels the MSB as bit 0, whereas the ESSI labels the LSB as bit 0.

Therefore, when using a standard codec, the ESSI MSB (or codec bit 0) is shifted in

first. The RSHFD bit should be cleared.

12.8.9.3 Receive Clock Polarity (RSCKP)—Bit 13

This bit controls which bit clock edge is used to capture data for the receive section.

•

0 = Captured data during clock falling edge

•

1 = Capture data input during rising edge of the clock

12.8.9.4 Receive DMA Enable (RDMAE)—Bit 12

This bit allows the ESSI to request a Direct Memory Access (DMA) module transfer of received

data.

If the receive FIFO is disabled:

•

0 = No DMA transfer is requested.

•

1 = A DMA request is generated when the ESSI Receive Data Ready (RDR) bit is set.

If the receive FIFO is enabled:

•

0 = No DMA transfer is requested.

•

1 = A DMA request is generated when the ESSI Receive FIFO Full (RFF) bit in the SSR is

set. The Receive FIFO Full Watermark should be set to RFWM = 01 because any other

setting of RFWM can leave data in the FIFO not transferred by the DMA.

Receive Interrupt Enable (RIE) has higher priority than Receive DMA Enable (RDMAE). That is

to say, if RIE is set, an interrupt is generated to the CPU instead of DMA.

Note:

If DAM is not supported on the chip, this bit has no meaning and should always be

cleared.

DSP56857 Datasheet(PDF) 344 Page - Freescale Semiconductor, Inc

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