DSP56857 datasheet(334/662 Pages) FREESCALE

334 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-34

Freescale Semiconductor

12.8.7.11 Receive Overrun Error (ROE)—Bit 5

This flag bit is set when the Receive Shift Register (RXSR) is enabled, filled, ready to transfer to

the SRX, or the RXFIFO registers, and when these registers are already full. If the Receive FIFO

is enabled, it is indicated by the Receive FIFO Full (RFF) bit otherwise this is indicated by the

Receive Data Ready (RDR) bit being set. The RXSR is not transferred in this case.

Note:

When using the RXFIFO with a watermark other than eight, the ROE bit does not

mean data has been lost. The RXCNT field of the SFCSR should be checked to

determine the likelihood of actual data loss.

A Receive Overrun Error (ROE) does not cause interrupts. However, when the ROE bit is set, it

causes a change in the interrupt vector used, allowing the use of a different interrupt handler for a

receive overrun condition. If a receive interrupt occurs with the ROE bit set, the receive data with

exception status interrupt is generated. If a receive interrupt occurs with the ROE bit cleared, the

Receive Data Interrupt is generated. The ROE bit is cleared by Power-On Reset (POR) or ESSI

reset (ESSIEN = 0) and by reading the SSR with the ROE bit set followed by reading the SRX

12.8.7.12 Transmitter Underrun Error (TUE)—Bit 4

This flag bit is set when the TXSR is empty, or when there is no data to be transmitted, indicated

by the TDE bit being set and a transmit time slot occurs. When a Transmit Underrun Error

occurs, the previously sent data is retransmitted.

A transmit time-slot in the Normal mode occurs when the frame sync is asserted. Each time-slot

requires data transmission in the Network mode, it may cause a TUE error.

The TUE bit does not cause interrupts. However, the TUE bit will cause a change in the interrupt

vector used for transmit interrupts. Consequently, a different interrupt handler can be used for a

transmit underrun condition. If a transmit interrupt occurs with the TUE bit set, the transmit data

with exception status interrupt is generated. If a transmit interrupt occurs with the TUE bit

cleared, the transmit data interrupt is generated.

The TUE bit is cleared by Power-On Reset (POR) or ESSI reset (ESSIEN = 0). The TUE bit is

also cleared by reading the SSR with the TUE bit set, followed by writing to the STX register or

to the STSR.

The state of this bit reflects the status of the transmitter(s) selected by the TXSF0-2 control bits in

the SCR4 register.

DSP56857 Datasheet(PDF) 334 Page - Freescale Semiconductor, Inc