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DSP56857 Datasheet(PDF) 471 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 471 Page - Freescale Semiconductor, Inc

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JTAG Port Architecture
JTAG Port, Rev. 4
Freescale Semiconductor
17-9
functionality. Data latched into the BSR during the Capture-DR controller state may not
match the drive state of the package signal if the system requiring pull-ups are not present
within the test environment.
2. The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR
output cells (PRELOAD) prior to selection of the CLAMP or EXTEST instruction. This
initialization ensures known data appears on the outputs when executing EXTEST. The
data held in the Shift register stage is transferred to the output latch on the falling edge of
TCK in the update Data Register (DR) controller state. Data is not presented to the pins
until the CLAMP or EXTEST instruction is executed.
Note:
Since there is no internal synchronization between the JTAG clock (TCK) and the
system Clock (CLK), some form of external synchronization to achieve meaningful
results when sampling system values using the SAMPLE/PRELOAD instruction must
be provided.
17.5.2.1 Identification Code Instruction (IDCODE)
The IDCODE instruction enables the IDREGISTER between TDI and TDO. It is provided as a
public instruction to allow the manufacturer part number and version of a component to be
determined through the TAP.
17.5.2.2 TAP Linking Module Select (TLM_SEL)
TLM_SEL instruction is a user-defined JTAG instruction. It is used to disable the Master TAP
and enable the TAP Linking Module (TLM). The TLM provides a means of connecting one or
more TAPs in a multi-TAP design, responding to the IC’s test pins in IEEE 1149.1 scan
operations. TLM serves as a community data register used to set the TAP linking configuration
desired. The TLM register is a 4-bit register, illustrated in Figure 17-3, and enabled between TDI
and TDO during a shift Data Register (DR) operation. It is updated on the Update DR operation.
Table 17-3. TLM Register
Update DR (Load)
Shift DR (Capture)
Bit
Master TAP
N/A
0
56800E TAP
N/A
1
N/C
N/A
2
N/C
N/A
3



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