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DSP56857 Datasheet(PDF) 469 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 469 Page - Freescale Semiconductor, Inc |
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469 / 662 page  JTAG Port Architecture JTAG Port, Rev. 4 Freescale Semiconductor 17-7 The 5685x includes four public instructions: 1. CLAMP 2. HIGHZ 3. IDCODE 4. TLM_SELECT The eight bits B[7:0] of the IR, decode the nine instructions, illustrated in Figure 17-2 and its data provided in Table 17-2. All other encodings are reserved. Figure 17-2. JTAGIR Register CAUTION Reserved JTAG instruction encodings should not be used. Hazardous operation of the chip could occur if these instructions are used. Table 17-2. Master TAP Instructions Opcode Instruction Target Register Opcode EXTEST Boundary 00000000 BYPASS Bypass 11111111 SAMPLE_PRELOAD Boundary 00000001 IDCODE IDCode 00000010 TLM_SEL TLM 00000101 HIGHZ Bypass 00000110 CLAMP Bypass 00000111 Reserved Reserved 00000011 Reserved Reserved 00000100 Reserved Reserved 00001000 IR 7 6 5 4 3 2 1 0‘ Read/Write B7 B6 B5 B4 B3 B2 B1 B0 Reset 000 0001 0 |
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