DSP56857 datasheet(465/662 Pages) FREESCALE

465 / 662 page

Introduction

JTAG Port, Rev. 4

Freescale Semiconductor

17-3

17.1 Introduction

This chapter describes the 56F800E core-based family of chips, providing board and chip-level

debugging and high-density circuit board testing specific to Joint Test Action Group (JTAG).

The 5685x provides board and chip-level testing capability through two on-chip modules, both

accessed through the JTAG port/EOnCE module interface:

•

Enhanced On-chip Emulation (EOnCE) module

•

Test Access Port (TAP) and 16-state controller, also known as the JTAG port

Presence of the JTAG port/EOnCE module interface permits insertion of the DSC chip into a

target system while retaining debug control. This capability is especially important for devices

without an external bus, because it eliminates the need for an expensive cable to bring out the

chip footprint required by a traditional emulator system.

The Enhanced OnCE (EOnCE) module is used in Digital Signal Controller (DSC) chips to debug

application software employed with the chip. The port is a separate on-chip block allowing

non-intrusive DSC interaction with accessibility through the pins of the JTAG interface. The

EOnCE module makes it possible to examine registers, memory, or on-chip peripherals’ contents

in a special debug environment. This avoids sacrificing any user-accessible, on-chip resources to

perform debugging procedures. Please refer to the DSP56F800E Core-Based Reference Manual

(DSP56800ERM)for details about implementation of the 5685x EOnCE module.

The JTAG port is a dedicated user-accessible TAP compatible with the IEEE 1149.1a-1993

Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing

high-density circuit boards have led to the development of this proposed standard under the

sponsorship of the Test Technology Committee of IEEE and the JTAG. 5685x supports circuit

board test strategies based on this standard.

Six dedicated pins interface to the TAP containing a 16-state controller. The TAP uses a

boundary scan technique to test the interconnections between integrated circuits after they are

assembled onto a Printed Circuit Board (PCB). Boundary scans allow observation and control

signal levels at each component pin through a Shift register placed next to each pin. This is

important for testing continuity and determining if pins are stuck at a one or zero level.

DSP56857 Datasheet(PDF) 465 Page - Freescale Semiconductor, Inc