DSP56857 datasheet(466/662 Pages) FREESCALE

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Features

5685X Digital Signal Controller User Manual, Rev. 4

17-4

Freescale Semiconductor

17.2 Features

Features of the Test Access Port (TAP) port include:

•

Perform boundary scan operations to test circuit board electrical continuity

•

Bypass the TAP for a given circuit board test by replacing the Boundary Scan Register

(BSR) with a single-bit register

•

Sample system pins during operation and transparently shift-out the results in the BSR

•

Preload output pins prior to invoking the EXTEST instruction

•

Disable the output drive to pins during circuit board testing

•

Provide a means of accessing the EOnCE module controller and circuits to control a target

system

•

Query the IDCODE from any TAP in the system

•

Force test data onto the peripheral outputs while replacing its BSR with a single bit

•

Enable/disable pull-up devices on peripheral boundary scan pins

17.3 Master Test Access Port (TAP)

The Master TAP consists of:

•

Synchronous finite 16-bit state machine

•

Eight-bit Instruction Register (IR)

•

Chip Identification (CID) register

•

Bypass (BYPASS) register

•

Boundary Scan Register (BSR)

Please see Figure 17-1 for additional information.

17.3.1 Signal Description

As described in IEEE 1149.1a, the JTAG port requires a minimum of four pins to support TDI,

TDO, TCK, and TMS signals. The 5685x also uses the optional TRST input signal and the DE

output signal used by the EOnCE module interface. Pin functions are described in Table 17-1.

DSP56857 Datasheet(PDF) 466 Page - Freescale Semiconductor, Inc

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