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DSP56857 Datasheet(PDF) 531 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 531 Page - Freescale Semiconductor, Inc |
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531 / 662 page  Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 4 Freescale Semiconductor B-29 9 of 24 ITCN Interrupt Priority Register 5 (IPR5) Bits Name Description 15 - 14 HOST_XMIT IPL SCI Receive Full Interrupt Priority Level This bit field is used to set the interrupt priority levels for this peripheral IRQ. 00 IRQ disabled by default 01 IRQ is priority level 0 10 IRQ is priority level 1 11 IRQ is priority level 2 13 - 12 HOST_RCV IPL SCI Receive Error Interrupt Priority Level This bit field is used to set the interrupt priority levels for this peripheral IRQ. 00 IRQ disabled by default 01 IRQ is priority level 0 10 IRQ is priority level 1 11 IRQ is priority level 2 11 - 10 SCI0_RCV IPL SCI Receive Idle Interrupt Priority Level This bit field is used to set the interrupt priority levels for this peripheral IRQ. 00 IRQ disabled by default 01 IRQ is priority level 0 10 IRQ is priority level 1 11 IRQ is priority level 2 9 - 8 SCI0_RERR IPL SCI0 Transmitter Idle Interrupt Priority Level This bit field is used to set the interrupt priority levels for certain peripheral IRQs. 00 IRQ disabled by default 01 IRQ is priority level 0 10 IRQ is priority level 1 11 IRQ is priority level 2 Interrupt Priority Register 5 (IPR5) $1FFF20 + $5 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read HOST_XMIT IPL HOST_RCV IPL SCI0_RCV IPL SCI0_RERR IPL SC0_RIDL IPL SCI0_TDL IPL SCI0_XMIT IPL SPI_XMIT IPL Write Reset 000 0000 00000 0000 See the following page for continuation of this register |
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