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DSP56857 Datasheet(PDF) 557 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 557 Page - Freescale Semiconductor, Inc |
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557 / 662 page ![]() Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 4 Freescale Semiconductor B-55 3 of 9 SCI SCI Control Register (SCICR) continued Bits Name Description 9 PE Parity Enable This bit enables the parity function. When enabled, the function replaces the most significant bit of the data character with a parity bit. 0 Parity function disabled 1 Parity function enabled 8 PT Parity Type This bit determines if the SCI generates and checks for even or odd parity of the data bits. 0 Even Parity 1 Odd parity 7 TEIE Transmitter Empty Interrupt Enable This bit enables Transmit Data Register Empty (TDRE) flag to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled 6 TIIE Transmitter Idle Interrupt Enable This bit enables the Transmitter Idle (TIDLE) flag to generate interrupt requests. 0 TIDLE interrupt requests disabled 1 TIDLE interrupt requests enabled 5 RFIE Receiver Full Interrupt Enable This bit enables the Receive Data Register Full (RDRF) flag, or the Overrun (OR) flag to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled SCI Control Register (SCICR) Base + $1 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read LOOP SWAI RSRC M WAKE POL PE PT TEIE TIIE RFIE REIE TE RE RWU SBK Write Reset 000000 0000000 000 See the following page for continuation of this register |
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