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DSP56857 Datasheet(PDF) 564 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 564 Page - Freescale Semiconductor, Inc |
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564 / 662 page ![]() Application: Date: Programmer: Sheet C 5685X Digital Signal Controller User Manual, Rev. 4 B-62 Freescale Semiconductor 1 of 6 SPI SPI Status and Control Register (SPSCR) SPI Status and Control Register (SPSCR) $1FFFE8 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SPR DSO ERRIE MODFEN SPRIE SPMSTR CPOL CPHA SPE SPTIE SPRF OVRF MODF SPTE Write Reset 0 1 1 0 0 0 0 1 01 00 00 00 Bits Name Description 15 - 13 SPR SPI Baud Rate These are read/write bits while in Master mode, selects one of four baud rates. 12 DSO Data Shift Order This read/write bit determines whether the MSB or LSB bit is transmitted or received first. 0 MSB transmitted first (MSB->LSB) 1 LSB transmitted first (LSB->MSB) 11 ERRIE Error Interrupt Enable This read/write bit enables the MODF and OVRF bits to generate interrupt requests. Reset clears the ERRIE bit. ERRIE bit enables both the MODF and OVRF bits to generate a receiver/error interrupt request. 0 MODF and OVRF cannot generate interrupt requests 1 MODF and OVRF can generate interrupt requests 10 MODFEN Mode Fault Enable This read/write bit when set to one allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. 9 SPRIE SPI Receiver Interrupt Enable This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set when a full data length transfers from the Shift Register to the Receive Data Register. 0 SPRF interrupt requests disabled 1 SPRF interrupt requests enabled 8 SPMSTR SPI Master This read/write bit selects Master mode operation or slave mode operation. 0 Slave mode 1 Master mode denotes Reserved Bits See the following page for continuation of this register |
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