DSP56857 datasheet(565/662 Pages) FREESCALE

565 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-63

2 of 6

SPI

SPI Status and Control Register (SPSCR) continued

SPI Status and

Control Register

(SPSCR)

$1FFFE8

Bits

15 14 13

Read

SPR

DSO ERRIE MODFEN SPRIE SPMSTR CPOL CPHA SPE SPTIE

SPRF OVRF MODF SPTE

Write

Reset

1000

000

Bits

Name

Description

CPOL

Clock Parity

This read/write bit determines the logic state of the SCLK pin between transmissions. To transmit

data between SPI modules, the SPPI modules musts have identical CPOL values.

Falling edge of SCLK starts transmission

Rising edge of the SCLK starts transmission

CPHA

Clock Phase

This read/write bit controls the timing relationship between the serial clock and SPI data. To

transmit data between SPI modules, there must be identical CPHA values. When CPHA = 0, the

SS pin of the Slave SPI module musts be set to Logic 1 between full length data transmissions.

SPE

SPI Enable

This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. When

setting/clearing this bit, no other bits in the SPSCR should be changed. Failure to following this

statement may result in spurious clocks.

SPI module disabled

SPI module enabled

SPTIE

SPI Transmit Interrupt Enable

This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a full

data length transfers from the Transmit Data Register to the Shift Register.

SPTE interrupt requests disabled

SPTE interrupt request enabled

SPRF

SPI Receiver Full

This read-only flag enables interrupt requests generated by the SPTE bit.

Receive Data Register not full

Receive Data Register full

denotes Reserved Bits

See the following page for continuation of this register

DSP56857 Datasheet(PDF) 565 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 565 Page - Freescale Semiconductor, Inc

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