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M24128-BW, M24128-BR, M24256-BW, M24256-BR

Table 15. AC Characteristics (M24128-BR, M24256-BR)

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Test conditions specified in Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock Frequency

400

kHz

Clock Pulse Width High

600

ns

Clock Pulse Width Low

1300

ns

Clock Rise Time

300

ns

Clock Fall Time

300

ns

SDA Rise Time

20

300

ns

SDA Fall Time

20

300

ns

Data In Set Up Time

100

ns

Data In Hold Time

0

ns

Data Out Hold Time

200

ns

Clock Low to Next Data Valid (Access Time)

200

900

ns

Start Condition Set Up Time

600

ns

Start Condition Hold Time

600

ns

Stop Condition Set Up Time

600

ns

Time between Stop Condition and Next Start

Condition

1300

ns

Write Time

10

ms