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PIC18F4520E/MLQTP Datasheet(PDF) 290 Page - Microchip Technology

Part # PIC18F4520E/MLQTP
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  390 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4520E/MLQTP Datasheet(HTML) 290 Page - Microchip Technology

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PIC18F2420/2520/4420/4520
DS39631A-page 288
Preliminary
 2004 Microchip Technology Inc.
GOTO
Unconditional Branch
Syntax:
GOTO k
Operands:
0
≤ k ≤ 1048575
Operation:
k
→ PC<20:1>
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
GOTO
allows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO
is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
INCF
Increment f
Syntax:
INCF
f {,d {,a}}
Operands:
0
≤ f ≤ 255
d
∈ [0,1]
a
∈ [0,1]
Operation:
(f) + 1
→ dest
Status Affected:
C, DC, N, OV, Z
Encoding:
0010
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT,
1, 0
Before Instruction
CNT
=
FFh
Z=
0
C=
?
DC
=
?
After Instruction
CNT
=
00h
Z=
1
C=
1
DC
=
1



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