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PIC18F4520E/MLQTP Datasheet(PDF) 302 Page - Microchip Technology

Part # PIC18F4520E/MLQTP
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  390 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4520E/MLQTP Datasheet(HTML) 302 Page - Microchip Technology

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PIC18F2420/2520/4420/4520
DS39631A-page 300
Preliminary
 2004 Microchip Technology Inc.
RLNCF
Rotate Left f (No Carry)
Syntax:
RLNCF
f {,d {,a}}
Operands:
0
≤ f ≤ 255
d
∈ [0,1]
a
∈ [0,1]
Operation:
(f<n>)
→ dest<n + 1>,
(f<7>)
→ dest<0>
Status Affected:
N, Z
Encoding:
0100
01da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
=
1010 1011
After Instruction
REG
=
0101 0111
register f
RRCF
Rotate Right f through Carry
Syntax:
RRCF
f {,d {,a}}
Operands:
0
≤ f ≤ 255
d
∈ [0,1]
a
∈ [0,1]
Operation:
(f<n>)
→ dest<n – 1>,
(f<0>)
→ C,
(C)
→ dest<7>
Status Affected:
C, N, Z
Encoding:
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RRCF
REG, 0, 0
Before Instruction
REG
=
1110 0110
C=
0
After Instruction
REG
=
1110 0110
W=
0111 0011
C=
0
C
register f



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