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PIC18F4520E/MLQTP Datasheet(PDF) 344 Page - Microchip Technology |
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PIC18F4520E/MLQTP Datasheet(HTML) 344 Page - Microchip Technology |
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344 / 390 page  PIC18F2420/2520/4420/4520 DS39631A-page 342 Preliminary 2004 Microchip Technology Inc. 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 Param. No. Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS + PLL Oscillator mode 5 33 kHz LP Oscillator mode 1TOSC External CLKI Period(1) 25 — ns EC, ECIO Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 10,000 ns XT Oscillator mode 40 100 250 250 ns ns HS Oscillator mode HS + PLL Oscillator mode 30 — µs LP Oscillator mode 2TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3TOSL, TOSH External Clock in (OSC1) High or Low Time 30 — ns XT Oscillator mode 2.5 — µs LP Oscillator mode 10 — ns HS Oscillator mode 4TOSR, TOSF External Clock in (OSC1) Rise or Fall Time — 20 ns XT Oscillator mode — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. |
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